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high voltage, quad - channel 12 - bit voltage output dac data sheet ad5504 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assume d by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or pate nt rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2009 - 2012 analog devices, inc. all rights reserved. technical support www.analog.com features quad - c hannel high voltage dac 12- bit resolution pin selectable 3 0 v or 6 0 v output range integrated precision refere nce low power serial interface with readback c apability integrated temperature sensor alarm fu nction power - on re set simultaneous updating via ldac wide operating temperature: ? 40 c to +10 5 c applications programmable voltage source s high v oltage led d river s receiver bias in optical communications general description the ad5504 is a quad - channel , 12- bit, serial input, digital - to - analog converter with on - chip high voltage output amplifiers and an integrated precision reference . the dac output voltage ranges are programmable via the range select pin ( r_sel ). if r_sel is held high , the dac output ranges are 0 v to 30 v. if r_sel is held low , the dac output ranges are 0 v to 60 v. the on - chip output amplifiers allow an output swing within the range of agnd + 0.5 v to v dd ? 0.5 v. the ad5504 has a high speed serial interface, which is com - patible with spi ? - , qspi ? - , microwire ? - , and dsp - interface standards and can handle clock speeds of up to 16.667 mhz. functional block dia gram 07994-001 power-on reset dgnd agnd sdo sclk sdi sync ldac alarm clr r_sel v logic v dd reference ad5504 daca input register a dac register a v outa + ? 1713k? 122.36k? 12 dac b input register b dac register b v outb + ? 1713k? 122.36k? 12 dac c input register c dac register c v outc + ? 1713k? 122.36k? 12 dac d input register d dac register d v outd + ? 1713k? 122.36k? 12 12 temperature sensor power-down control logic input control logic figure 1.
ad5504 data sheet rev. b | page 2 of 20 t able of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 4 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum rating s ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and fun ction descriptions ............................. 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 12 theory of operation ...................................................................... 14 power - up state ........................................................................... 14 power - down mode .................................................................... 14 dac channel architecture ....................................................... 14 selecting the output range ...................................................... 14 clr function .............................................................................. 14 ldac function .......................................................................... 14 temperature sensor ................................................................... 15 power dissipation ....................................................................... 15 power supply sequencing ......................................................... 15 serial interface ................................................................................ 16 write mode ................................................................................. 16 read mode .................................................................................. 16 writing to the control register ................................................ 16 interfacing examples ................................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 12/ 12 rev . a to rev. b changes to t 4 parameter, table 4 .................................................... 6 changes to figure 3 and figure 4 ................................................... 7 changes to pin 3 description, table 7 and pin 4 description, table 7 ................................................................................................ 9 changes to write mode section ................................................... 16 changes to table 10 ........................................................................ 17 10/ 1 0 rev . 0 to rev. a changes to figure 3 and figure 4 ................................................... 7 7 /0 9 rev ision 0: initia l version
data sheet ad5504 re v. b | page 3 of 20 the serial interface offers the user the capability of both writing to, and reading from, most of the internal registers. to reduce power consumption at power up, only the digital section of the ad5504 is powered up initially. this gives the u ser the ability to program the dac registers to the required value while typically only consuming 30 a of supply current. the ad5504 incor - porates power - on reset circuitry that ensures the dac registers power up in a known condition and remain there until a valid write to the device has taken place. the analog section is powered up by issuing a power - up command via the spi interface. the ad5504 provides software - selectable output loads while in the power - down mode. the ad5504 has an on - chip temperature se nsor. when the temperature on the die exceeds 110 c, the alarm pin (an active low cmos output pin) flags an alarm and the ad5504 enters a temperature power - down mode disconnecting the output amplifier thus removing the short - circuit condi tion. the ad5504 remains in power - down mode until a software power - up command is executed. the ad5 504 is available in a compact 16 - lead tssop. the ad5504 is guaranteed to operate over the extended temperature range of ?40c to +105c. table 1 . related device part no. description ad5501 high voltage, 12 - bit voltage output dac
ad5504 data sheet rev. b | page 4 of 20 specifications v dd = 10 v to 62 v; v logic = 2.3 v to 5.5 v ; r l = 6 0 k ; c l = 200 pf ; ? 40c < t a < + 10 5c, unless otherwise noted . table 2 . parameter symbol min typ 1 max unit test conditions/comments accuracy 2 resolution 12 bits differential nonlinearity dnl ?1 1 lsb integral nonlinearity inl 60 v m ode ?2 + 2 lsb v dd = 62 v 30 v m ode ?3 + 3 lsb v dd = 62 v v outx temperature coefficient 3 , 4 , 5 50 ppm/c dac code = half scale zero - scale error v zse 100 mv dac code = 0 zero - scale error drift 4 60 v/c 60 v mode offset error 6 v o e ?80 + 120 mv offset error drift 4 60 v/c 60 v mode full - scale error v fse ?325 + 275 mv full - scale error drift 4 1 mv/c ? 40c to +25c; 60 v mode 350 v/c +25c to +105c; 60 v mode gain error ?0.6 + 0.6 % of f sr gain temperature coefficient 4 10 ppm of fsr/c 60 v mode dc crosstalk 4 r l = 60 k? to agnd or v dd due to single channel full - scale output change 3 mv 60 v mode due to powe ring down (per channel) 4 mv 60 v mode output characteristics output voltage range 7 agnd + 0.5 v dd ? 0.5 v short - circuit curren t 4 , 8 2 ma on any single channel capacitive load stabilit y 4 1 v to 4 v step r l = 60 k? to 1 nf load current 4 ?1 + 1 ma on any single channel dc output impedance 4 3 ? dc output leakage 4 10 a digital inputs input logic high v ih 2.0 v v logic = 4.5 v to 5.5 v 1.8 v v logic = 2.3 v to 3.6 v input logic low v il 0.8 v v logic = 2.3 v to 5.5 v input current i il 1 a input capacitance 4 i ic 5 pf digital outputs output high voltage v oh v logic ? 0.4 v v i source = 200 a output low voltage v ol dgnd + 0.4 v v i sink = 200 a three - s tate leakage current sdi, sdo, sclk, ldac , clr , r_sel ?1 +1 a alarm ?10 +10 a output capacitance 4 5 pf
data sheet ad5504 re v. b | page 5 of 20 parameter symbol min typ 1 max unit test conditions/comments power supplies v dd 10 62 v v logic 2.3 5.5 v quiescent supply current (i quiescent ) 2 3 ma stati c conditions; dac outputs = mid scale logic supply current (i logic ) 0.4 2 a v ih = v logic ; v il = dgnd dc psrr 4 dac output = full - scale 60 v m ode 68 db 30 v m ode 76 db power - down mode supply c urrent i dd_pwd software power -d own mode 30 50 a junc tion temperature 8 t j 130 c t j = t a + p total ja 1 typical specifications represent average readings at 25 c, v dd = 62 v and v logic = 5 v. 2 valid in output voltage range of (v dd ? 0.5 v) to (agnd + 0.5 v). outputs are unloaded. 3 includes linearity, offset, and gain drift. 4 guaranteed by design and characterization. not production tested. 5 v outx refers to v outa , v outb , v outc , or v outd . 6 dac code = 32 for 60 v mode ; dac code = 6 4 for 30 v mode. 7 the dac architecture gives a fixed linear voltage output range of 0 v to 30 v if r_sel is held high and 0 v to 60 v if r_sel is held low. as the output voltage range is limited by output amplifier comp liance , v dd should be set to at least 0.5 v higher than the maximum output voltage to ensure compliance. 8 if the die temperature exceeds 110 c, the ad5504 enters a temperature power - down mode putting the dac outputs into a high impedance state thereby rem oving the short - circuit condition. overheating caused by long term short - circuit condition(s) is detected by an integrated thermal sensor. after power - down, the ad5504 stays powered down until a software power - up command is executed. ac characteristics v dd = 10 v to 62 v; v logic = 2.3 v to 5.5 v ; r l = 6 0 k? ; c l = 200 pf ; ?40c < t a < + 105 c, unless otherwise noted. table 3 . parameter 1 , 2 min typ max unit test conditions/comments 3 ac characteristics output voltage settling time ? to ? scale settling to 1 lsb , r l = 60 k? 60 v m ode 45 55 s 30 v m ode 25 35 s slew rate 0.6 5 v/s digital -to - analog glitch e nergy 300 nv -s 1 lsb change around major carry in 60 v mode glitch impulse peak amplitude 170 mv 60 v mode digital feedthrough 4 0 nv -s digital crosstalk 5 nv -s analog crosstalk 600 nv -s dac -to - dac crosstalk 600 nv -s peak -to - peak noise 140 v p -p 0.1 hz to 10 hz ; dac code = 0x800 4 m v p -p 0.1 hz to 10 k hz ; dac code = 0x800 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range i s ?40c to + 10 5c, typical at 25c.
ad5504 data sheet rev. b | page 6 of 20 timing characteristics v dd = 30 v , v logic = 2.3 v to 5.5 v and ? 4 0 c < t a < +1 0 5c ; a ll specifications t min to t max , unless otherwise noted. table 4 . parameter limit 1 unit test conditions/comments t 1 2 6 0 ns min sclk cycle time t 2 10 ns min sclk high time t 3 1 0 ns min sclk low time t 4 25 ns min sync falling edge to sclk risi ng edge setup time t 5 1 5 ns min data setup time t 6 5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 2 0 ns min minimum sync high time t 9 20 ns min ldac pulse width low t 1 0 5 0 ns min sclk fall ing edge to ldac rising edge t 1 1 1 5 ns min clr pulse width low t 1 2 100 ns typ clr pulse activation time t 1 3 20 s typ a l a r m clear time t 14 1 1 0 ns min sclk cycl e time in read mode t 1 5 3 5 5 ns max sclk rising edge to sdo valid t 1 6 3 2 5 ns min sclk to sdo d ata hold time t 1 7 4 5 0 s max power - on r eset time ( this is not shown in the timing diagrams ) t 18 5 5 0 s max power - on time ( this is not shown in the timing diag rams ) t 19 5 s typ a l a r m clear to output amplifier turn on ( this is not shown in the timing diagrams ) 1 all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 16.667 mhz. 3 under load conditions shown in figure 2. 4 time fr om when the v dd /v logic supplies are power ed- up to when a digital interface command can be executed. 5 time required from execution of power - on software command to when the dac outputs have settled to 1 v. v oh (min) ? v ol (max) 2 200a i ol 200a i oh to output pin c l 50pf 07994-002 figure 2. load circuit for sdo timing diagram
data sheet ad5504 re v. b | page 7 of 20 1 asynchronous ldac update mode. 2 synchronous ldac update mode. 3 in the event of overtemperature condition. 4 v outx refers to any of v outa , v outb, v outc or v outd . sclk sdi r/w t 8 t 4 clr sync d0 ldac 1 ldac 2 alarm 3 v outx 4 t 3 t 2 t 1 t 7 t 6 t 5 t 9 t 10 t 11 t 12 t 13 07994-003 figure 3. write timing di agram sclk sync sdi sdo t 14 d 11 d 0 r/w a2 a1 a0 x x d 10 d 9 d 8 d 1 d 2 x x x x t 15 t 16 07994-004 x figure 4 . read timing diagram
ad5504 data sheet rev. b | page 8 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch - up. table 5 . parameter rating v dd to agnd ? 0.3 v, + 64 v v logic to dgnd ? 0.3 v to +7 v v out x to agnd 1 ? 0.3 v to v dd + 0.3 v digital in put to dgnd ? 0.3 v to v logic + 0.3 v sdo output to dgnd ? 0.3 v to v logic + 0.3 v agnd to dgnd ? 0.3 v to + 0.3 v maximum junction temperature (t j m ax imum ) 150 c st orage temperature range ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature range 20 sec to 40 sec 1 v outx refers to v outa , v outb , v outc , or v outd . stresses above those listed under absolute maximum ratings may cause per manent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. thermal r esistance is for a jedec 4 - layer(2s2p) board. table 6 . thermal resistance package type ja unit 16-l ead tssop 112.60 c/w esd caution
data sheet ad5504 re v. b | page 9 of 20 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 sync sclk sdi agnd dgnd sdo clr ldac 16 15 14 13 12 11 10 9 alarm v dd r_sel v outc v outd v outb v outa v logic top view (not to scale) ad5504 07994-005 figure 5. pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the i nput register and the dac register are set to 0x000 and the outputs to zero scale. 2 sync falling edge synchroni z ation s ignal. this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register and data is tran sferred in on the ris ing edges of the following clocks. the selected dac register is updated on the 16th falling sclk , unless sync is taken high before this edge, in which case , the rising edge of sync acts as an interru pt, and the write sequence is ignored by the dac. 3 sclk serial clock input. data is clocked into the input shift register on the rising edge of the serial clock input. data can be transferred at rates up to 16 mhz. 4 sd i serial data input. this part has a 16 - bit shift register. data is clocked into the register on the rising edge of the serial clock input. 5 sdo serial data output. cmos output. this pin s erves as the readback function for all dac and c ont r ol registers. data is clocked out on the risi ng edge of sclk and is valid on the fall ing edge of sclk . 6 dgnd digital ground pin. 7 agnd analog ground pin. 8 ldac load dac input. pulsing this pin low allows any or all dac registers to be updated if the i nput register s have new data . this allows all dac outputs to update simultaneously . alternatively, this pin can be tied permanently low. 9 v out d buffered analog output voltage from dac d . 10 v outc buffered analog output voltage from dac c . 11 v outb buffered analog output vol tage from dac b . 12 v outa buffered analog output voltage from dac a . 13 r_sel range select pin. tying this pin to dgnd selects a dac output range of 0 v to 60 v , alternatively tying r_sel to v logic select s a dac out put range of 0 v to 30 v. 14 v dd positive analog power supply . 10 v to 62 v for the specified performance. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 15 alarm active l ow cmos o utput p in. this pin f lags an alarm if the temperature on the die exceeds 1 1 0 c. 16 v logic logic power supply; 2.3 v to 5. 5 v. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors.
ad5504 data sheet rev. b | page 10 of 20 typical performance characteristics 0.8 ?0.8 ?0.4 0 0.4 32 1008 2048 3056 4064 inl (lsb) code 07994-006 figure 6. typical inl 0.50 ?0.50 ?0.25 0 0.25 32 1008 2048 3056 4064 dnl (lsb) code 07994-007 figure 7 . typical dnl 15.0050 14.9950 14.9975 15.0000 15.0025 0 0.05 0.10 0.15 0.20 v outx (v) time (ms) 07994-008 figure 8 . output settling time (high to low) 0 0.05 0.10 0.15 0.20 v outx (v) time (ms) 45.0025 45.0000 44.9975 44.9950 44.9925 07994-009 figure 9 . output settling time (low to high) 0 2.5 5.0 7.5 10.0 output voltage (v) time (seconds) 200 100 0 ?100 ?200 v dd = 62v v outx = 30v 07994-010 figure 10 . ou tput noise 0 15 30 45 60 i dd (ma) v outa (v) 0.70 0.65 0.60 0.55 0.50 07994-011 v dd = 62v v outb , v outc , and v outd powered down figure 11 . i dd vs. v outa
data sheet ad5504 re v. b | page 11 of 20 0 15 45 30 60 i dd (ma) output voltage (v) 2.2 1.8 1.9 2.0 2.1 v dd = 62v v outa = v outb = v outc = v outd 07994-012 figure 12 . i dd vs. v outa to v outd 0 5 10 15 amplitude (lsb) time (ms) 2 ?10 ?8 ?6 ?4 ?2 0 07994-013 figure 13 . digital - to- analog negative glitch impulse 0 5 10 15 amplitude (lsb) time (ms) 12 ?4 ?2 0 2 4 6 8 10 07994-014 figure 14 . digi tal - to- analog positive glitch impulse 0 2 6 4 10 8 v outa (v) time (s) 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 07994-202 v outa = 30v; v outb switching v outb = 0v to 30v v outb = 0v to 45v v outb = 0v to 60v figure 15 . dac - to- dac c rosstalk ?1.0 ?0.5 0.5 0 1.0 lsbs load current (ma) 6 0 1 2 3 4 5 07994-201 v outd v outb v outc v outa figure 16 . dac - to- dac m ismatch
ad5504 data sheet rev. b | page 12 of 20 terminology relative accuracy for the dac, relative accuracy , or i ntegral n onlinearity (i nl) , is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity differential n onlinearity (dnl) is the difference between the measured change and the ideal 1 ls b change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono - tonic by desig n. zero - code error zero - code error is a measure of the output error when zero code (0x000) is loaded into the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the ad5504 becaus e the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero - code error is expressed in millivolts . zero - code error drift zero - code error drift is a measure of the change in zero - code error with a change in temperature. it is expressed in v/c . offset error a measure of the difference between v out (actual) and v out (ideal) expressed in millivolts in the linear region of the transfer function. offset error is measured on the ad5 504 with c ode 32 loaded in the dac register s for 60 v mode and with c ode 64 loaded in the dac register s for 30 v mode . offset error is expressed in millivolts . offset error drift offset error drift is a measure of the change in offset error with a change in temperature. it is expressed in v/c . full - scale error full - scale error is a measure of the output error when full - scale code ( 0xfff ) is loaded in to the dac register. full - scale error is expressed in m illivolts . full - scale error drift full - scale error drift is a measure of the change in full - scale error with a cha nge in temperature. it is expressed in v/c . gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal , expressed as a percent age of the full - scale range. gain temperature coefficient the gain temperatu re coeffic ient is a measure of the change in gain with changes in temperature. it is expressed in (ppm of full - scale range)/c. digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s and is measured when the digital input code is changed by 1 lsb at the major carry transition . dc and ac power supply rejection ratio (psrr) psrr indicates h ow the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v outa , v outb , v outc , or v outd to a change in v dd for full - scale output of the dac. it is measured in decibels . for dc psrr, v dd is dc varied 10%. for ac psrr, v dd is ac varied 10%. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) whi le monitoring another dac kept at midscale. it is expressed in millivolts . dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma . digital fe edthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the d igital input pins of the device but is measured when the dac is not being written to ( sync held high). it is specified in nv - s an d m easured with a full - scale change on the digital input pins, that is , from all 0s to all 1s or vice versa. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is me asured by loading one of the i nput register s with a full - scale code change (all 0s to all 1s or vice versa) while keeping ldac high , and then pulsing ldac low and monitor ing the output of the dac whose digital code has n ot changed. the area of the glitch is expressed in nv - s.
data sheet ad5504 re v. b | page 13 of 20 dac -to - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes b oth digital and analog crosstalk. it is measured by loading one of the dacs with a full - scale code change (all 0s to all 1s or vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv - s. c apacitive load stability capacitive load stability refers to the ability of the amplifier to drive a capacitive load. an amplifier output is considered s table if any overshoot or ringing has stopped before approx imately 1.5 times the s ettling time of the dac has elapsed.
ad5504 data sheet rev. b | page 14 of 20 theory of operation the ad5504 contains four dacs, four output amplifiers , and a precision reference in a single package. the architecture of a s ingle dac channel consists of a 12- bit resistor string dac followed by an output buffe r amplifier. the part operates from a single - supply voltage of 10 v to 62 v . the dac output voltage range is selected via the range select, r_sel , pin. the dac output range is 0 v to 30 v if r_sel is held high and 0 v t o 60 v if r_sel is held low . data is written to the ad5504 in a 16- bit word format (see table 8 ), via a serial interface. power - u p s tate on power - up , the power - on re set circuitry clear s the bits of the control register to 0 x40 (see table 10) . this ensures that the analog section is initially powered down, which helps reduce power consumption . t he user can program the dac registers to the required values while typically consuming only 30 a of supply current. the power - on reset circuitry also ensures that all the input and dac registers power up in a known condition, 0x 0 00, and remain there until a valid write to the device has taken place. the analog section can be powered up by setting any or all of bit c2 to bit c5 of the c ontrol register to 1. p ower - d own mode each dac channel can be individually powered up or powered down by programming the c ontrol register (see table 10 ). when the dac channel is powered down , t he associated analog circuitry turn s off to reduce power consumption. the digital section of the ad5504 remains powered up. the output of the dac amplifier can be three - stated or connected to agnd via an internal 20 k ? resistor , depending on the state of b it c6 in the c ontrol register . the power - down mode does not change the contents of the dac register to ensure that the dac channel return s to its previous voltage when the power - down bit is set to 1. the ad5504 also offers the user the flexibility of upd ating the dac re gisters during power - down. the c ontrol register can be read back at any time to check the status of the bits. dac c h annel a r chitecture the architecture of a single dac channel consists of a 12- bit resistor string dac followed by an output b uffer amplifier (see figure 17 ). the resistor string section is simply a string of resistors, each of value r from v ref gener ated by the precision reference to agnd. this type of architecture guarantees dac monotonicity . the 12 - bi t binary digital code loaded to the dac register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. t he output amplifier multipli es the dac output voltage to give a fixed linear voltage output range of 0 v to 60 v if r_sel = 0 or 0 v to 30 v if r_sel = 1. each output ampl ifier is capable of driving a 6 0 k ? load while allowing an output swing w ithin the range of a gnd + 0.5 v and v dd ? 0.5 v. because the dac archi tecture gives a fixed voltage output range of 0 v to 3 0 v or 0 v to 60 v , t he user should set v dd to at least 3 0.5 v or 6 0.5 v to use the maximum dac resolution. the data format for the ad5501 is straight binary and the output voltage follows the formula range d v out = 4096 where: d is the code loaded to the dac. range = 30, if r_sel is high, and 60 if r_sel is low. gain v outx dac register input register precision reference agnd 12 12 dac 07994-015 figure 17 . dac channel architecture (single - channel shown) selecting t he out put range the output range of the dacs is selected by the r_sel pin. when the r_sel pin is connected to l ogic 1 , the dac output voltages can be set between 0 v and 30 v . when the r_sel pin is connected to l ogic 0 , the dac output voltages can be set between 0 v and 60 v . the state of r_sel can be changed any time when the seria l interface is not being used, that is, not during a read or write operation. when the r_sel p in is changed, the voltage on the output pin remain s the same until the next write to the dac register (and ldac is brought low). for example, if the user writes 0 x 800 to the dac register when in 30 v mode ( r_sel = 1) , t he output voltage is 15 v (assuming ldac is low or has been pulsed low). when the user switches to 60 v mode ( r_sel = 0) , the output stay s at 15 v until the user writes a new value to the dac register. lda c must be low or be pulsed low for the output to change. clr function the ad5504 has a hardware clr pin that is an asynchronous clear input. the clr input is falling edge sensitive. bringing the clr line low clears the contents of the i nput register and the dac registers to 0x000. th e clr pulse activation time , that is, the falling edge of clr to when the output starts to change , i s typically 100 n s. ldac function the dac outputs can be updated using the hardware ldac pin. ldac is normally high. on the falling edge of ldac , data is copied from the i nput register s to the dac regi sters , and the dac outputs are updated simultaneously ( a synchronous update mode, see figure 3 ). if the ldac is kept low, or is low on the falling edge of the 16 th sclk , the appropriate dac register and dac output are updated automatically ( s ynchronous update mode, see figure 3 ).
data sheet ad5504 re v. b | page 15 of 20 temperature s ensor the ad5504 has an integrated temperature sensor that causes the part to enter thermal shutdown mode when the temperature on the d ie exceeds 110 c. in the rmal shutdown mode, the analog section of the device powers down and the dac outputs are disconnected , but the digital section remains operational, which is equivalent to setting the power - down bit in the control register . to indicate that the ad 5504 has entered temperature shutdown mode, b it 0 of the control register is set to 1 and the alarm pin goes low . the ad550 4 remains in temperature shutdown mode with bit 0 set to 1 an d the alarm pin low , even if the die temperature falls, until b it 0 in the control register is cleared to 0. power dissipation drawing current from any of the voltage output pins cause s a temperature rise in the die and package of the ad5504. the package junction temperature ( t j ) should not exceed 130c for normal operation. if the die temperature exceeds 110c , the ad5504 enter s thermal shutdown mode as described in the temperature s ensor section. the amount of heat generated can be calculated using the formula t j = t a + ( p total ja ) where: t j is the package junction temperature . t a is the ambient temperature . p total is the total power being consumed by the ad5504 . ja is the thermal impedance of the ad5504 package (see the absolute maximum ratings sectio n for this value). power supply sequenc ing the power supplies for the ad550 4 can be applied in any order without affecting the device. however, the agnd and dgnd pins should be connected to the relevant ground plane before the power supplies are applied. n one of the digital input pins (sclk, sdi, sync , r_sel and c lr ) should be allowed to float during power up. the digital input pins can be connected to pull - up (to v logic ) or pull - down (to dgnd) resistors as required.
ad5504 data sheet rev. b | page 16 of 20 s erial interface the ad5504 has a serial interface ( sync , sclk, sdi , and sdo), which is compatible with spi interface standards , as well with as most dsps. the ad5504 allows writing of data , via the serial interface , to the i nput and c ontrol register s. t he dac register s are not directly writeable or readable. the input shift register is 16 bits wide (see table 8 ). the 16 - bit word consists of one read/write (r/ w ) control bit, fol lowed by three address bits and 12 dac data bits. data is loaded msb first. write mode to write to a register , the r/ w bit should be 0. the three address bits in the input register (see table 9 ) then determine th e register to update. the address bits (a 2 to a0) are used for either dac register selection or for writing to the c ontrol register . data is clocked into the selected register during the remaining 12 clocks of the same frame. figur e 3 shows a timin g diagram of a typical ad5504 write sequence. the write sequence begins by bringing the sync line low. d ata on the sdi line is clocked into the 16 - bit shift register on the ris ing edge of sclk. on the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (that is, a change in the selected dac/dacs i nput register /registers or a change in the m ode of operation ) . the ad5504 does not require a continuous sclk and dynamic power can be saved by transmitting clock pulses during a serial write only . at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a min imum of 20 ns before the next write sequence for a falling edge of sync to initiate the next write sequence. operate a ll interface pins close to the supply rails to minimize power consumption in the digital input buffers. r ead m ode the ad 5504 allows data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the dac registers. t o read back a register, it is first necessary to tell the ad5504 that a readback is requir ed. this is achieved by setting the r/ w bit to 1. the three address bits then determine the register from which data is to be read back. data from the selected register is then clocked out of the sdo pin on the next twelve clocks of the s ame frame. the sdo pin is normally three - stated but becomes driven on the rising edge of the fifth clock pulse. the pin remains driven until the data from the register has been clocked out or the sync pin is returned high. figure 4 shows the timing requirements during a read operation. note that due to timing requirements of t 1 4 ( 1 1 0 ns) , the maximum speed of the spi interface during a read op eration should not exceed 9 mhz . writing to the control register the c o ntrol register is written when b its [db14: db12 ] are 1. the c ontrol register set s the power - up state of the dac output s . a write to the c ontrol register must be followed by another write operation. the second write operation can be a write to a dac input reg ister or a nop write. figure 18 shows some typical combinations. table 8 . input register bit map db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r/ w a2 a1 a0 dat a table 9 . input register bit functions bit description r/ w indicates a read from or a write to the addressed register . a2, a1, a0 these bits determine if the i nput register s or the c ontrol register are to be ac cessed. a2 a1 a0 function/address 0 0 0 n o o peration 0 0 1 dac a i nput register 0 1 0 dac b i nput register 0 1 1 dac c i nput register 1 0 0 dac d i nput register 1 0 1 write d ata contents to all four dac in put register s 1 1 0 reserved 1 1 1 control register d11:d0 data b its
data sheet ad5504 re v. b | page 17 of 20 table 10. control register functions db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 r/ w 1 1 1 0 0 0 0 0 c6 c5 c4 c3 c2 c1 c0 1 read - only bit. this bit should be 0 when writing to the control register. table 11. control register function bit descriptions bit no. bit name description db 0 c0 c0 = 0: the device is not in thermal shutdown mode. c0 = 1: the device is in thermal shu tdown mode. db 1 c1 c1 = 0: reserved. this bit should be 0 when writing to the control register. db 2 c2 1 c2 = 0: dac channel a power - down (default). c2 = 1: dac channel a power - up. db 3 c3 1 c3 = 0: dac channel b power - down (default). c3 = 1: dac cha nnel b power - up. db 4 c4 1 c4 = 0: dac channel c power - down (default). c4 = 1: dac channel c power - up. db 5 c5 1 c5 = 0: dac channel d power - down (default). c5 = 1: dac channel d power - up. db 6 c6 c6 = 0: outputs connected to agnd through a 20 k ? resistor (default). c6 = 1: output s are three - stated. 1 if bit c2 to bit c 5 are set to 0 , the part is placed in power - down mode . 07994-120 write n write n + 1 write to control register nop write to control register write to dac register write n + 2 write to control register write to control register nop write to control register write to control register write to dac register figure 18 . control register write sequences
ad5504 data sheet rev. b | page 18 of 20 interfacing examples the spi int erface of the ad5 504 is designed to allow it to be easily connected to industry - standard dsps and microcon - trollers. figure 19 s hows how the ad5504 can be connected to the analog devices, inc., black fin ? d s p. the black fin has an integrated spi port that can be connected directly to the spi pins of the ad5504. p rogrammable input/output pins are also available and can be used to read or set the state of the digital input or output pins associated with the interface. spiselx adsp-bf531 ad5504 sck mosi miso pf10 pf8 pf9 pf7 sync sclk sdi sdo r_sel clr ldac alarm 07994-016 figure 19 . interfacing to a blackfin dsp the analog devices adsp - 21065l is a floating point dsp with two serial ports (sports). figure 20 shows how one sport can b e used to control the ad5504 . in this example, the transmit frame synchronization (tfs) pin is connected to the receive frame synchro nization (rfs) pin. t he transmit and receive clocks (tclk and rclk) are also connected together. the user can write to the ad 5504 by writing to the transmit register. when a read operation is performed , the data is clocked out of the ad5504 on the last 12 sclks. the dsp receive interrupt can be used to indicate when the read operation is complete. sync sclk sdi sdo r_sel clr ldac alarm ad5504 adsp-21065l tfsx rfsx tclkx rclkx dtxa drxa flag 0 flag 1 flag 2 flag 3 07994-017 figure 20 . interfacing to an adsp - 21065l dsp
data sheet ad5504 re v. b | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 21 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 temperature range package descriptio n package option ad5504 b ruz ?40c to +105c 16- lead thin shrink small outline package [ tssop ] ru -16 AD5504BRUZ - reel ?40c to +105c 16- lead thi n shrink small outline package [ tssop ] ru -16 eval - ad5504ebz evaluation board 1 z = rohs compliant part . .
ad5504 data sheet rev. b | page 20 of 20 notes ? 2009 - 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07994 - 0 - 12/12(b)

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